1. Field of the Invention
This invention relates to the fabrication of complementary metal-oxide-semiconductor (CMOS) circuit structures on an insulator substrate, such as silicon-on-sapphire (SOS), and more particularly to a process for forming devices such as field effect transistors (FETs) having a highly controlled defect density profile in the channel region.
2. Description of the Related Art
The advantages of utilizing a composite substrate comprised of a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulated substrate are well recognized. These advantages include a substantial reduction in parasitic capacitance between charged active regions, and the effective elimination of leakage currents flowing between adjacent active devices. This is accomplished by employing as the substrate an insulative material with a high dielectric constant, such as sapphire (Al.sub.2 O.sub.3), and providing that the conduction path of any interdevice leakage current must pass through the substrate.
In a typical prior fabrication technique for an FET, a thin undoped silicon layer was deposited on top of a sapphire substrate and etched into separate islands, or mesas. The islands intended for p-channel devices were then covered with a photoresist while a p-type dopant such as boron was implanted into the islands for the n-channel devices; the process was then reversed, with the n-channel devices covered with a photoresist while the p-channel islands were implanted with an n-type dopant such as phosphorus or arsenic. The photoresist was then removed, oxide and metallic (or polysilicon) layers deposited over the gate area, source and drain areas implanted, and gate, source and drain contacts formed on the islands.
The dopant implant has generally been performed with an ion implanter. The implant is activated by a high temperature anneal, such as 900.degree. C. for 20-30 minutes, which also reduces the damage caused by the implant. The nature of the dopant implant influences at least three of the ultimate device parameters: it establishes the threshold voltage for turning on the FET; it determines the punchthrough voltage for short channel transistors, and it controls the leakage current through the transistor along its back gate interface with the sapphire substrate.
With conventional SOS techniques, the crystalline quality of the silicon near the sapphire substrate is usually not as good as it is farther from the sapphire, and contains a significantly higher concentration of lattice defects. This results from the fact that, although the lattice spacings of silicon and sapphire are similar, they are not identical. This causes an undesirably high concentration of defects when the silicon is grown over the sapphire. As a result, the dopant implants in the defect area are not activated as efficiently, and a greater concentration of dopant has to be implanted to obtain the same level of electrically active atoms than with higher quality silicon. Another distinct problem associated with conventional CMOS/SOS devices is a tendency toward leakage current between the source and drain along the edges of the island near the sapphire substrate because of the higher defect concentration in that area. This creates a parasitic transistor which has a lower threshold voltage than desired, and turns on before the gate voltage has reached the designed threshold level; this problem is particularly acute for n-channel devices. Back gate leakage current across the silicon-sapphire interface is also a problem.
The back gate and edge leakage currents described above tend to increase during irradiation, and are a major cause of CMOS/SOS circuit failure in radiative environments. Even if the device operates satisfactorily in a normal environment, it would be desirable to make it more "radiation hard".
A technique for significantly reducing the semiconductor lattice defect concentration near the insulator substrate is described in U.S. Pat. No. 4,509,990 by Prahalad K. Vasudev, issued Apr. 9, 1985 to Hughes Aircraft Company, the assignee of the present invention. This patent discloses a "solid phase epitaxy" method for improving the quality of the semiconductor layer throughout an entire wafer, particularly near its interface with an insulator substrate. Prior to the formation of individual circuit devices, an ion species is implanted into the semiconductor layer along the entire wafer at an implant energy and dosage which is sufficient to amorphize a buried layer portion of the semiconductor to a depth near the insulator substrate. The amorphous buried layer is then regrown by a high temperature anneal so as to recrystallize the buried layer, using the overlying unamorphized portion of the semiconductor layer as a crystallization seed. In this manner the semiconductor lattice structure is made more homogeneous throughout. The semiconductor layer is then etched into separate islands, and circuit devices are formed using conventional techniques.
This solid phase epitaxy technique can provide consistently good circuit structures if the thickness of the semiconductor layer is perfectly uniform and known. Unfortunately, with present deposition techniques random variations occur in the thickness of the semiconductor film at different locations on the wafer. Thus, for a constant ion species implant designed to create a buried amorphous layer which extends down to the nominal (target) thickness of the semiconductor film, the implanted ions will not amorphize the semiconductor all the way down to the substrate wherever the semiconductor layer is thicker than nominal, leaving a film of defective semiconductor near the underlying insulator substrate. On the other hand, with an SOS structure using an amorphizing silicon implant, if the silicon layer is thinner than nominal a substantial portion of the implanted silicon ions will travel into the sapphire, causing a release of aluminum from the sapphire back into the silicon. While this is not a major drawback for n-channel devices, the aluminum "auto doping" is a significant problem for p-channel devices. It negates the doping of the p-channel devices, and also increases the severity of back channel leakage.
The former solution to this problem has been to avoid implanting the silicon ions to the full nominal thickness of the silicon layer. While this reduces the problem of aluminum auto doping for p-channel devices, it may leave more residual lattice defects in the silicon near the sapphire substrate. Thus, in order to overcome the increase in back channel current, some of the original benefits of the solid phase epitaxy technique may have been traded off.